1. Field of the Invention
The present invention generally relates to a dual damascene processing method, and more particularly relates to a dual damascene processing method utilizing a silicon rich oxide (SRO) layer as an etching stop layer thereof and its structure.
2. Description of the Prior Art
As the level of integration of integrated circuits increases, the integrated circuits (IC) design becomes smaller and smaller in the MOS manufacture process. Besides, under the urgent demand of the faster transmission speed, integrated circuits devices utilizing copper as metal interconnections can bear the higher integrated circuits array so as to deeply reduce the number of the interconnections reduce the manufacture cost and improve the calculating speed of the computer, and can obtain a better metal reliability. Hence, devices utilizing copper as the interconnections can provide the advantages of longer product lift and reliability.
When the metal-oxide-semiconductor (MOS) manufactures get into the very large scale integrated circuits (VLSI) technique, the metallization process becomes an important and key process. As the level of integration of IC devices increases and the critical dimension shrinks, the current density of devices simultaneously increases to cause many problem of the metal interconnections. Usually, copper deposited by chemical vapor deposition (CVD) method is applied to fill via contact via hole or used as the interconnections in IC devices. However, owing to the dual damascene process can replace the conventional plasma etching method to obtain the metal copper conductor, so as the dual damascene technique is gradually become an important step of the metallization process. In the dual damascene process, a conventional dry etching process is performed to complete the plug, such as a vertical conductor, and the trench for connection. After, using the chemical vapor deposition method is to fill into a barrier layer and then also to fill into a copper membrane material. Last, performing a chemical mechanism polishing step is to obtain a flat surface and to simultaneously complete the vertical and horizontal connection of the conductor.
The point of another technique of the dual damascene process mentioned above is the etching technique for etching the trench for filling the metal conductor. In the preceding process of the dual damascene process, there are two conventional methods for forming the trench of the dual damascene structure. One process method is utilizing the silicon nitride (SiN) layer as the etching stop layer between the upper dielectric layer and the lower dielectric layer in the step of etching the trench via contact. The process method using the silicon nitride layer as the etching stop layer has some disadvantages of the problem of the high dielectric constant index (K) of the intermetal dielectric (IMD) resulting in the high capacitance (C) of the dielectric and causing the noise of the dielectric to obtain a bad isolating effect of the dielectric. Another process method does not utilize the etching stop layer in the step of etching the trench via contact. However, the process method has disadvantages of bad controlling of the trench profile and depth, so it will easily cause the difficult in the manufacturing process.
Obviously, the main spirit of the present invention is to provide a dual damascene processing method using a silicon rich oxide (SRO) layer thereof, and then some disadvantages of well-known technology are overcome.
The primary object of the present invention is to provide a dual damascene processing method using a silicon rich oxide (SRO) layer thereof so as to obtain a better trench profile and a better depth control. Besides, the present invention does not to increase the dielectric constant index (K) of the inter metal dielectric (IMD).
Another object of the present invention is to use the silicon rich oxide layer as the etching stop layer in the dual damascene process so as the present invention can achieve a better trench microloading and better bottom profile
Further object of the present invention is to improve the function and operation speed of the devices without increasing the processing difficult in the manufacturing process.
In order to achieve previous objects, the present invention sequentially forms a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to form a trench and a via hole and then to obtain a dual damascene structure profile having the trench and the via hole.
Other aspects, features, and advantages of the present invention will become apparent, as the invention becomes better understood by reading the following description in conjunction with the accompanying drawings.